Many different types of circuits and systems have been developed in the past for reading and writing data into a DRAM which comprises a predetermined number of rows and columns of individual memory cells. One such system is disclosed, for example, in U.S. Pat. No. 5,148,546, entitled "Method and System for Minimizing Power Demands on Portable Computers and the Like by Refreshing Selected DRAM Ceils" and issued to Greg A. Blodgett. This patent is assigned to the present assignee and is incorporated herein by reference.
In the past, it was customary to use the conventional 0.0 and 5 volt digital logic levels to define the logic swing for accessing these DRAM cells. More recently, DRAM access level translating circuitry has been developed which operates to convert the above 0.0 to 5 volt logic swing down to 3 volts used in switching these access transistors in order to conserve power in the DRAM. This level translating circuitry also serves to reduce certain metal-oxide-silicon (MOS) processing requirements, such as reducing MOS gate oxide thicknesses which were required to handle to the larger 0.0 to 5 volt logic swing. Thus, this level translating circuitry is operative to convert the 0.0 to 5 volt logic swing to a 0.0 to 3 volt logic swing prior to writing data into the DRAM. Further the level translator circuit is operative to convert the 0.0 to 3 volt logic swing back to a 0.0 to 5 volt logic swing in the process of reading data from the DRAM and applying it to external circuitry to boost a gate voltage of an NPN output buffer transistor in order to drive a full supply potential of the output buffer to an output node. In the present example if V.sub.cc is 3 volts the gate voltage is boosted to 5 volts by a level translator. In a further example if V.sub.cc is 5 volts the gate voltage is boosted to 7 volts.
This level translating circuitry is normally connected in one of two signal paths used for reading data from a DRAM and when operating in the well known "Extended Data Out" mode for video RAMs (VRAMs) or for synchronous DRAMs or "SDRAMs". Using this mode of operation, the elimination of crossing currents in output MOS buffer transistors is particularly critical since the output data can switch states with no shut off period in between.
Access circuitry for reading data from the DRAM will typically include a large plurality of data channels, e.g. sixteen, each of which includes a pair of parallel connected data processing control lines or paths. One of these paths will include the above level translating stage used for converting the 3 volt logic swing to a 5 volt logic swing and then applying it to an output pull up MOS buffer transistor. This output pull up MOS transistor is normally connected in series to an MOS pull down transistor and between a V.sub.cc supply voltage and ground potential. The common node interconnecting the pull up and the pull down transistors is the point where the output signal from each channel is taken, and the pull down transistor is connected to be driven by the second control line or signal processing path which in turn is connected in parallel with the level translating stage.
These level translating stages in each read channel introduce time delays into the signals being processed in this one signal path of each channel and thereby make it necessary to introduce an even longer time delay in the other parallel signal path of each signal channel which feeds the pull down MOS transistor in the output driver stage. This latter requirement is necessary in order to ensure that the above pull up and pull down transistors in the output driver stage are not conducting at the same time, and that their crossing or cross-over currents are minimized or eliminated.
The problem and disadvantage of using fixed delays in this other parallel signal path or control line driving the pull down transistor is that these fixed delays must always be longer than actually required in order to ensure that the pull down transistor is never turned on until the pull up transistor is completely turned off. This latter requirement is necessary as a result of variations in MOS wafer processing and MOS process tolerances, and it represents an undesirable time delay in accessing the DRAM. It also imposes an undesirable limitation on the maximum achievable switching speeds and data processing capability for this access circuitry. Accordingly, it is the solution to the above problems to which the present invention is directed.